The present invention relates to a semiconductor design technology, and more particularly, to a fuse set for outputting a redundancy address corresponding to accessing a target memory cell to be repaired.
An integration level of a semiconductor memory device has increased incredibly. Thus, a semiconductor memory device such as a Double Data Rate Synchronous DRAM (DDR SDRAM) includes more than thousands of memory cells. If one of the memory cells fails, a semiconductor memory device thereof cannot perform a desired operation. In probability, a very small number of memory cells fail due to advanced manufacturing technology of a semiconductor memory device. However, even if a semiconductor memory device includes a very small number of failed memory cells, the semiconductor memory device may be dismissed as a defective product. This is unacceptable in terms of product yields. In order to overcome the problem, a semiconductor memory device includes not only a normal memory cell but also a redundancy memory cell. If a normal memory cell fails, it is replaced with one of redundancy memory cells. Hereinafter, a failed normal memory cell that should be replaced with one of redundancy memory cells is referred to as a target memory cell to be repaired.
Meanwhile, a semiconductor memory device includes a fuse set for programming an address corresponding to a target memory cell to be repaired. Here, the programming is a set of processes for storing an address in a fuse set corresponding to a target memory cell to be repaired. The fuse set outputs a programmed address as a redundancy address. Therefore, in case of accessing a target memory cell to be repaired, a semiconductor memory device compares an address inputted corresponding to the target memory cell to be repaired with a redundancy address outputted from a fuse set and redirects it to the redundancy memory cell instead of the target memory cell to be repaired.
An electric cutting-off method and a laser cutting method were used to program a plurality of fuses. Here, the electric cutting method cuts off a target fuse by applying excessive current to and melting down the target fuse. The laser cutting-off method cuts off a target fuse by blowing the target fuse using a laser beam. In general, the electric cutting-off method was widely used because the electric cutting-off method is simpler than the laser cutting-off method.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes a memory bank 110, a column decoder 130, and a plurality of fuse sets 150.
The memory bank 110 includes first to nth memory cell arrays each of which is a group of a plurality of memory cells where n is a natural number. Each of the first to nth memory cell arrays 111, 112, and 113 includes a normal memory cell array and a redundancy memory cell array. The column decoder 130 decodes a column address applied from an external device and selects a corresponding memory cell based on the decoded column address. The fuse set 150 outputs a column address programmed corresponding to a target memory cell to be repaired as a redundancy address.
Hereinafter, an operation of a conventional semiconductor memory device when a target memory cell to be repaired is accessed will be described.
The semiconductor memory device activates a corresponding word line by decoding a row address. Then, a plurality of fuse sets 150 output address information programmed in response to a cell array activation signal MATY<1:n> (see FIG. 2), which is memory cell array information including the activated word line, as a redundancy address YRA<3:9> (see FIG. 2). The column decoder 130 outputs a selection signal to access a redundancy memory cell by comparing an address inputted corresponding to a target memory cell to be repaired with the redundancy address YRA<3:9>. Such a sequence of processes guarantees the semiconductor memory device to access a redundancy memory cell that normally operates when the semiconductor memory device performs a read operation and a write operation.
FIG. 2 is a circuit diagram illustrating a plurality of fuse sets 150 shown in FIG. 1. For convenience in description, a fuse set outputting a third redundancy address YRA<3> will be described as an example among a plurality of fuse sets.
Referring to FIG. 2, the fuse set includes a plurality of fuses 210, a plurality of selectors 230, a latch unit 250, a precharging unit 270, and an output unit 290.
The plurality of fuses 210 program address information corresponding to a target memory cell to be repaired. The plurality of fuses 210 include a node A and a first fuse to an nth fuse F1, F2, . . . , Fn connected to a plurality of selectors 230, respectively.
The plurality of selectors 230 include a first NMOS transistor to an nth NMOS transistor N1, N2, . . . , and Nn which form a source-drain path between the first to nth fuses F1, F2, . . . , and Fn and a ground supply voltage (VSS) terminal and have a gate receiving first to nth cell array activation signals MATY<1:n>. Here, the first to nth cell array activation signals MATY<1:n> are signals corresponding to a memory cell array including an activated word line among the first to the Nth memory cell arrays 111, 112, and 113 (see FIG. 1).
The latch unit 250 latches a logical level value according to a programming state of a selected fuse in response to the first to nth cell array activation signals MATY<1:n> among a plurality of fuses 210. The latch unit 250 includes a first inverter INV1 and a second inverter INV2.
The precharging unit 270 initializes the latch unit 250. The precharging unit 270 includes a first PMOS transistor P1 forming a source-drain path between an external supply voltage VDD terminal and a node A which is an input terminal of the latch unit 250 and a gate for receiving a reset signal RST. The reset signal RST is a signal transiting from a logical ‘low’ to logical ‘high’ when a semiconductor memory device is activated. The first PMOS transistor P1 is turned on before activating the semiconductor memory device and drives the nose A with external supply voltage VDD. The reset signal RST will be described again with reference to FIG. 3.
The output unit 290 receives an output signal of the latch unit 250 and outputs a third redundancy address YRA<3>. The output unit 290 includes a third inverter INV3 for receiving an output signal of the latch unit 250.
Meanwhile, each of the plurality of fuse sets 150 has the same structure described above and outputs a corresponding redundancy address. That is, a plurality of fuse sets 150 output programmed addresses as third to ninth redundancy addresses YRA<3:9> in response to the first to nth cell array activation signals MATY<1:n>. The semiconductor memory device performs an access operation of a redundancy memory cell using the outputted third to ninth redundancy addresses YRA<3:9>.
FIG. 3 is a timing diagram describing a circuit operation of a plurality of fuse sets 150 of FIG. 2. For convenience in description, a fuse set outputting a third redundancy address YRA<3> will be described as an example among the plurality of fuse sets 150. Also, the first fuse F1 will be exemplarily described among a plurality of fuses 210. That is, circuit operations when the first fuse F1 is cut off and when the first fuse F1 is not cut off will be described.
At first, a circuit operation when the first fuse F1 is cut off will be described.
Referring to FIGS. 2 and 3, the reset signal RST transits from logical ‘high’ to logical ‘low’ in response to a precharging command PRC. Therefore, the first PMOS transistor PM1 is turned on and the node A is driven with an external supply voltage VDD. Accordingly, the latch unit 250 is initialized to logical ‘high’. Then, when the active command ACT is applied, the reset signal RST transits from logical ‘low’ to logical ‘high’. The first PMOS transistor P1 is turned off, and the node A sustains logical ‘high’ by the second inverter INV2 of the latch unit 250. Meanwhile, the first cell array activation signal MATY<1> is activated from logical ‘low’ to logical ‘high’ in response to the active command ACT. Here, although the first NMOS transistor N1 is turned on, the node A sustains logical ‘high’ because the first fuse F1 is cut off.
Hereinafter, a circuit operation when the first fuse F1 is not cut off will be described. The circuit operation before the active command ACT will be omitted because it is identical to that when the first fuse F1 is cut off. The first cell array activation signal MATY<1> is activated from logical ‘low’ to logical ‘high’ in response to the active command ACT. The first NMOS transistor N1 is turned on and the node A transits from logical ‘high’ to logical ‘low’ because the first fuse F1 is not cut off.
FIG. 3 is a timing diagram illustrating operations when a fuse set normally operates. As shown, a logical level of a third redundancy address YRA<3> is decided according to whether the first fuse F1 is cut off or not. That is, the third redundancy address YRA<3> becomes logical ‘high’ when the first fuse F1 is cut off and the third redundancy address YRA<3> becomes logical ‘low’ when the first fuse F1 is not cut off. The third redundancy address YRA<3> is compared with an address applied corresponding to a read command RD and a semiconductor memory device decide whether or not to access a redundancy memory cell according to the comparison result.
Meanwhile, when the first fuse F1 is cut off, a current path if formed between the node A and an external supply voltage VDD terminal by the second PMOS transistor P2 of the second inverter INV2. The formed current path is referred to as a pull-up current path. That is, the node A sustains logical ‘high’ because the node A is driven with a pull-up driving current I_PU flowing through the pull-up current path. When the first fuse F1 is not cut off, a current path (hereinafter pull-down current path) is formed between the node A and the ground supply voltage VSS terminal as well as the pull-up current path. That is, the node A is driven by current generated oppositely by the pull-up driving current I_PU and a pull-down driving current I_PD flowing through the pull-down current path. In ideal case, the node A transits to logical ‘low’ because the pull-down driving current I_PD is greater than the pull-up driving current I_PU.
Meanwhile, according to the development of a fabrication technology of a semiconductor memory device, a very small scale design-rule such as a sub-micron level design-rule has been applied to design an internal circuit of a semiconductor memory device. Since a semiconductor memory device is densely integrated based on the sub-micron level design-rule, a typical chip has been decreasing in size rapidly. However, since such sub-micron level circuitry elements vary in properties according to manufacturing process characteristics, a supply voltage, and temperature variation, related problems have occurred.
FIG. 4 is a timing diagram illustrating malfunctioning of a plurality of fuse sets 150 of FIG. 2. For ease of description, signals identical to those shown in FIG. 3 will be described.
Referring to FIGS. 2 to 4, operation states of a semiconductor memory device vary according to the manufacturing process characteristics, supply voltage, and temperature variation. Accordingly, the pull-up driving current I_PU and the pull-down driving current I_PD may be changed. In other word, if the first cell array activation signal MATY<1> is activated without cutting off the first fuse F1, the node A of FIG. 3 is driven by a ground supply voltage VSS according to an increase of the pull-down driving current I_PD. However, in FIG. 4, the node A is not driven by the ground supply voltage VSS because the pull-down driving current I_PD does not become sufficiently greater than the pull-up driving current I_PU or because the pull-up driving current I_PU become excessively large. That is, a voltage level of the node A becomes vague. Finally, the vague voltage level of the node A makes an incorrect third redundancy address YRA<3> to output according to a threshold voltage of the first inverter INV1. Such an incorrect third redundancy address YRA<3> causes a problem of misreading an address corresponding to a normal memory cell as a target memory cell to be repaired or misreading an address corresponding to a target memory cell to be repaired as a normal memory cell.
As described above, a plurality of fuse sets 150 (see FIG. 1) form a pull-up driving path and a pull-down driving path including a corresponding fuse according to 0th to nth cell array activation signals MATY<1:n> and generate third to ninth redundancy addresses YRA<3:9> through the pull-up driving current I_PU and the pull-down driving current I_PD. However, the operation state changes according to variation of a manufacturing process, a supply voltage, and a temperature due to down-sized elements according to the development of a manufacturing technology. Such variation of the operation state becomes a critical factor to change the pull-up driving current I_PU and the pull-down driving current I_PU. The changed pull-up driving current I_PU and pull-down driving current I_PD make a plurality of fuse sets 150 to output incorrect third to ninth redundancy addresses YPA<3:9>.
The number of memory banks has increased in order to satisfy a demand of a user such as a mass capacity semiconductor memory device. If a semiconductor memory device has a plurality of fuse sets corresponding each of memory banks as shown in FIG. 1, the number of the fuse sets increases in proportion to the increment of the memory banks. That is, power consumption of the semiconductor memory device increases corresponding to the increment of the fuse sets.